// write everything at once
fvec_t tmp; tmp.data = o->buffer->data + o->write_pos; tmp.length = write;
fvec_t tmpin; tmpin.data = input->data; tmpin.length = write;
- assert(tmpin.length == tmp.length);
+ //assert(tmpin.length == tmp.length);
fvec_copy(&tmpin, &tmp);
//AUBIO_WRN("ringbuffer: push1: changing write_pos from %d\n", o->write_pos);
tmp.length = remaining;
tmpin.data = input->data;
tmpin.length = remaining;
- assert(tmpin.length == tmp.length);
+ //assert(tmpin.length == tmp.length);
fvec_copy(&tmpin, &tmp);
}
// write start
tmp.length = write - remaining;
tmpin.data = input->data + remaining;
tmpin.length = write - remaining;
- assert(tmpin.length == tmp.length);
+ //assert(tmpin.length == tmp.length);
fvec_copy(&tmpin, &tmp);
//AUBIO_WRN("ringbuffer: push2: changing write_pos from %d\n", o->write_pos);
o->write_pos += write;
}
uint_t aubio_ringbuffer_pull(aubio_ringbuffer_t *o, fvec_t *output, uint_t request) {
- if (o->available <= 0) {
+ if (o->available < (sint_t)request) {
AUBIO_ERR("ringbuffer: pull: requested %d but %d available\n",
request, o->available);
return AUBIO_FAIL;
// read everything at once
fvec_t tmp; tmp.data = o->buffer->data + o->read_pos; tmp.length = request;
fvec_t tmpout; tmpout.data = output->data; tmpout.length = request;
- assert(tmpout.length == tmp.length);
+ //assert(tmpout.length == tmp.length);
fvec_copy(&tmp, &tmpout);
//AUBIO_WRN("ringbuffer: pull1: changing read_pos from %d\n", o->read_pos);
o->read_pos += request;
tmp.length = remaining;
tmpout.data = output->data;
tmpout.length = remaining;
- assert(tmpout.length == tmp.length);
+ //assert(tmpout.length == tmp.length);
fvec_copy(&tmpout, &tmp);
// write start
tmp.data = o->buffer->data;
tmp.length = request - remaining;
tmpout.data = output->data + remaining;
tmpout.length = request - remaining;
- assert(tmpout.length == tmp.length);
+ //assert(tmpout.length == tmp.length);
fvec_copy(&tmp, &tmpout);
//AUBIO_WRN("ringbuffer: pull2: changing read_pos from %d\n", o->read_pos);
o->read_pos += request;